1. Field of the Invention
This invention relates to a method of the plasma cleaning of a chip-mounted board, which method is carried out before a wire bonding operation in which pads of a chip are connected respectively to electrodes of the board by wires. The invention also relates to apparatus for performing this method.
2. Related Art
There is known a technique in which the plasma cleaning of a board is carried out before a wire bonding operation in which pads of a semiconductor integrated circuit chip (hereinafter referred to merely as xe2x80x9cchipxe2x80x9d), mounted on the board, are connected respectively to electrodes of the board by wires. In the plasma cleaning, the board is received within a vacuum chamber, and a high-frequency voltage is applied to a plasma-generating electrode provided in the vacuum chamber so as to produce ions of positive charge and electrons of negative charge, and these ions and electrons are caused to impinge on the pads on an upper surface of the chip and the electrodes on the board, thereby cleaning these pads and electrodes. When the pads and the electrodes are thus cleaned, the wire bonding ability thereof is enhanced, and the wires can be firmly bonded to the pads and the electrodes.
However, when the above plasma cleaning of the board is carried out, a transistor structure portion within the chip is liable to be destroyed. The cause of this destruction has not yet been known, and this is one of the reasons why the plasma cleaning has not been extensively used. The present invention has been made in the process of clearing up the cause of this chip destruction, and the cause of the chip destruction, cleared up by the inventors of the present invention, will be explained in the following.
FIG. 5 is a cross-sectional view of an essential portion of a conventional apparatus for the plasma cleaning of a board. In this Figure, reference numeral 1 denotes the board to be subjected to the plasma cleaning. A land 2 is formed at a central portion of an upper surface of the board 1, and electrodes 3 are formed on the upper surface of the board 1, and are disposed around the land 2. A chip 4 is adhesively bonded to an upper surface of the land 2 by a bond (adhesive) 6. Pads 5 are formed on an upper surface of the chip 4. The pads 5 are connected respectively to the electrodes 3 by wires in a later wire bonding step. The pads 5 and the electrodes 3 are subjected to a plasma cleaning treatment so as to enhance the wire bonding ability.
The bond 6 is formed by mixing powder of metal, such as Ag, into an epoxy resin. After this board 1 is completed, it is incorporated into an electronic equipment, and when an electric current is caused to flow through the chip 4, heat is generated because of an internal resistance of the chip 4. Therefore, the bond 6 contains the powder of metal having good thermal conductivity, such as Ag, so that the heat, generated by the chip 4, can be transferred to the land 2 through the bond 6.
The board 1 is placed on a plate-like, plasma-generating electrode 7. A cover member 8 is provided to cover the plasma-generating electrode 7, and a vacuum chamber 9 is defined by the cover member 8 and the electrode 7. An AC power source 10 is connected to the plasma-generating electrode 7 so as to apply a high-frequency voltage to this electrode. The cover 8 is connected to a grounding portion 11. The vacuum chamber 9 is evacuated to a vacuum by vacuum evacuation means, and plasma-generating gas, such as argon (Ar) gas, is supplied into the vacuum chamber 9.
Next, the plasma cleaning operation will be described. The board 1 is placed on the plasma-generating electrode 7, and the vacuum chamber 9 is evacuated to a vacuum by the vacuum evacuation means, and then Ar gas is supplied into the vacuum chamber 9. Then, the AC power source 10 is driven to apply a high-frequency voltage to the electrode 7. As a result, the interior of the vacuum chamber 9 is in a plasma condition, and ions Ar+ of positive charge and electrons exe2x88x92 of negative charge are produced within the vacuum chamber 9. The ions Ar+ and the electrons exe2x88x92 impinge on the electrodes 3 of the board 1 and the pads 5 of the chip 4, thereby cleaning the electrodes 3 and the pads 5.
The board 1 is placed on a central portion of the plasma-generating electrode 7, and therefore a peripheral portion of this electrode 7 is not covered with the board 1, and is exposed to the vacuum chamber 9. On the other hand, the high voltage having a high frequency is applied to the electrode 7, so that the electrode 7 varies between a positive potential and a negative potential at a high frequency. As a result, the motion of the electrons exe2x88x92 becomes quite vigorous at the peripheral portion of the electrode 7. In FIG. 5, broken-line arrows a show the electrons exe2x88x92 vigorously moving at the peripheral portion of the electrode 7 which is not covered with the board 1. And besides, those electrons exe2x88x92, which are present at the central portion of the vacuum chamber 9 above the chip 4, avoid the board 1, and move toward the peripheral portion of the vacuum chamber 9 (as indicated by broken-line arrows b), and make a vigorous motion as indicated by the broken-line arrows a.
Because of the above phenomenon, the amount of the ions Ar+ of positive charge relatively increases at the central portion A of the vacuum chamber 9 while the amount of the electrons exe2x88x92 of negative charge relatively increases at the peripheral portion B of the vacuum chamber 9. Namely, the distribution of the positive ions and the electrons within the vacuum chamber 9 becomes uneven. Therefore, the pads 5 of the chip 4, located at the central portion A of the vacuum chamber 9, are liable to be electrically positively charged while the electrodes 3 of the board 1 are liable to be electrically negatively charged.
With respect to the destruction of the chip, it is important to note that the land 2 is negatively charged with the electrons exe2x88x92. More specifically, as shown in FIG. 5, the land 2 is much larger in size than the chip 4, and a peripheral portion C of the land 2 is extending outwardly of the chip 4, and is exposed, and the electrons exe2x88x92 impinge on this extending portion of the land 2 in a larger amount than the positive ions do, so that the land 2 is electrically negatively charged. On the other hand, the pads 5 of the chip 4 are positively charged as described aboved, and therefore a large potential difference occurs between the pads 5 and the land 2. However, since the chip 4 is adhesively bonded to the land 2 by the electrically-conductive paste 6, a large potential difference occurs between the pads 5 and the chip 4, and as a result, a charge build-up current flows through a transistor structure portion, formed within the chip 4, so that the transistor structure portion is destroyed by this current.
Next, explanation will be made of the relation between the size of the area of the extending (exposed) portion of the land 2, extending outwardly of the chip 4, and the potential difference between the pads 5 and the transistor structure portion. FIGS. 6A to 6D are plan views showing various examples of chip-land arrangements, respectively. More specifically, in FIG. 6A, a chip 4 and a land 2 are equal in area to each other, and the land 2 does not extend outwardly of the chip 4 at all (The extension area is 0 mm2). In FIG. 6B, the area of an extending, exposed portion of a land 2, extending outwardly of a chip 4, is relatively small (The extension area is 30 mm2). In FIG. 6C, a chip 4 has a relatively small size, and the area of an extending, exposed portion of a land 2, extending outwardly of the chip 4, is relatively large (The extension area is 100 mm2). The arrangement of FIG. 6D differs from the arrangement of FIG. 6C only in that a conducting portion 12 is connected to a land 2. This conducting portion 12 serves as a plating electrode when forming a circuit pattern, including the land 2 and electrodes 3, by plating means, and is commonly provided in a circuit board for the electronic devices. In this case, the conducting portion 12 is electrically connected to the land 2, and therefore the substantial extension area of the land 2 is the actual extension area thereof plus the area of the conducting portion 12 (The extension area is 170 mm2).
FIG. 7 is a graph showing a relation between the exposure area (extension area) of the land and the potential difference between the pads and the land. The four arrangements, shown respectively in FIGS. 6A to 6D, were subjected to plasma cleaning under the same conditions (A power of the high-frequency power source was 500 W, the pressure within the vacuum chamber was 6 Pa, and the plasm cleaning time was 1 minute), and the potential difference between the pads 5 and the chip 4 in each of the above arrangements was measured, and these results are shown in FIG. 7. In the case of FIG. 6A, the potential difference is 2.4 V, and in the case of FIG. 6B, the potential difference is 5.3 V, and in the case of FIG. 6C, the potential difference was 5.8 V, and in the case of FIG. 6D, the potential difference is 6.2 V.
As is clear from FIG. 7, the larger the exposure (extension) area, extending outwardly of the chip 4, is, the larger the potential difference between the pads 5 and the chip 4 is, and therefore with the increase of this potential difference, a larger charge build-up current flows, thereby increasing the possibility of the chip destruction. The upper limit of the potential difference, at which the chip destruction occurs, varies depending on the kinds of chips, but generally, when the potential difference exceeds 5 V, the possibility of the chip destruction abruptly increases. It has been found through experiments by the inventors of the present invention that particularly those chips, having MOS transistors, are liable to be destroyed.
From the foregoing, the inventors of the present invention has found the following facts (1) and (2):
(1) The cause of the chip destruction during the plasma cleaning is that the distribution of the ions of positive charge and the electrons of negative charge, produced within the vacuum chamber during the plasma cleaning, is not uniform, so that the pads of the chip are positively charged while the land, on which the chip is mounted, is negatively charged, with the result that an excess charge build-up current flows through the transistor structure portion in the chip.
(2) The potential difference between the pads and the chip is generally proportional to the area of the extending, exposed portion, extending outwardly of the chip, plus the area of the conducting portion connected to the land.
It is therefore an object of this invention to provide a method of the plasma cleaning of a chip-mounted board, in which the destruction of a chip due to the charge build-up in a land during the plasma cleaning is prevented.
Another object of the invention is to provide apparatus for performing this plasma-cleaning method.
According to one aspect of the present invention, a mask member, having openings, is superposed on a board received within a vacuum chamber, in such a manner that an exposed portion of a land, extending outwardly of a chip, and a conducting portion, connected to the land, are covered with the mask member, with the chip and electrodes of the board exposed respectively through the openings. In this condition, a voltage is applied to a plasma-generating electrode so as to produce ions of positive charge and electrons of negative charge within the vacuum chamber, so that the ions and the electrons impinge on pads of the chip and the electrodes of the board in such a manner that the electrons impinge on the electrodes of the board in a relatively larger amount than the ions do, thereby cleaning the pads and the electrodes.
According to another aspect of the invention, a chip is adhesively mounted on a land with an electrically-insulating paste, and a voltage is applied to a plasma-generating electrode so as to produce ions of positive charge and electrons of negative charge within a vacuum chamber, so that the ions and the electrons impinge on pads of the chip and the electrodes of the board in such a manner that the electrons impinge on the electrodes of the board in a relatively larger amount than the ions do, thereby cleaning the pads and the electrodes.
With the above construction of the present invention, the exposed portion of the land, extending outwardly of the chip, is prevented from being negatively charged up with the electrons, or the chip and the land are electrically insulated from each other. By doing so, a large charge build-up current is prevented from flowing through the chip during the plasma cleaning, thereby preventing the chip from being destroyed.